SH7265 Datasheet, PDF (1319/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Bit
Bit Name
15
BSTS
14
SUREQ
Section 25 USB 2.0 Host/Function Module (USB)
Initial
Value
0
0
R/W
R
R/W*²
Description
Buffer Status
Indicates whether DCP FIFO buffer access is
enabled or disabled. The direction of access,
reading or writing, is determined by the ISEL bit in
CFIFOSEL.
0: Buffer access is disabled.
1: Buffer access is enabled.
Setup Token Transmission
Setting this bit to 1 transmits a setup packet.
After completing the setup transaction process, this
module generates either the SACK or SIGN
interrupt and clears this bit to 0.
Before setting this bit to 1, set the DEVSEL bits,
USBREQ register, USBVAL register, USBINDX
register, and USBLENG register appropriately to
transmit the desired USB request in the setup
transaction.
Before setting this bit to 1, check that the PID bits
for the DCP are set to NAK.
0: Invalid
1: Transmits the setup packet.
Note: After setting this bit to 1, do not modify the
DEVSEL bits, USBREQ register, USBVAL
register, USBINDX register, or USBLENG
register until the setup transaction is
completed (SUREQ = 1).
Write 1 to this bit only when transmitting the
setup token; for the other purposes, write 0.
Rev. 1.00 Mar. 14, 2008 Page 1283 of 1984
REJ09B0351-0100