SH7265 Datasheet, PDF (1694/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 33 Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
4
MSTP74 1
R/W Module Stop 74
When set to 1, the clock supply to the FLCTL is halted.
0: FLCTL runs.
1: Clock supply to FLCTL is halted.
3
MSTP73 1
R/W Module Stop 73
When set to 1, the clock supply to the SSU0 is halted.
0: SSU0 runs.
1: Clock supply to SSU0 is halted.
2
MSTP72 1
R/W Module Stop 72
When set to 1, the clock supply to the SSU1 is halted.
0: SSU1 runs.
1: Clock supply to SSU1 is halted.
1
MSTP71 1
R/W Module Stop 71
When set to 1, the clock supply to the Video IN/2DG/Video
OUT is halted.
0: Video IN/2DG/Video OUT run.
1: Clock supply to Video IN/2DG/Video OUT is halted.
0
MSTP70 1
R/W Module Stop 70
When set to 1, the clock supply to the USB is halted.
0: USB runs.
1: Clock supply to USB is halted.
Rev. 1.00 Mar. 14, 2008 Page 1658 of 1984
REJ09B0351-0100