SH7265 Datasheet, PDF (334/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
11 to 9 DPCG
[2:0]
Undefined R/W
Row Precharge Interval Setting
These bits specify the minimum interval that must elapse
between the SDRAM deactivation (PRA) command and
the next valid command.
000: 1 cycle
:
111: 8 cycles
8
DWR
Undefined R/W Write Recovery Interval Setting
This bit specifies the interval that must elapse between
the SDRAM write command (WRITE) and deactivation
(PRA).
0: 1 cycle
1: 2 cycles
7 to 3 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
2 to 0 DCL[2:0] Undefined R/W SDRAM Controller Column Latency Setting
These bits specify the column latency of the SDRAM
controller. This setting only affects the latency setting on
the SDRAM controller side. To specify the column latency
for externally connected SDRAM, it is necessary to use
the SDRAMm mode register (SDmMOD), which is
described later.
000: Setting prohibited
001: 1 cycle
010: 2 cycles
011: 3 cycles
1xx: Setting prohibited
[Legend]
x: Don't care
Rev. 1.00 Mar. 14, 2008 Page 298 of 1984
REJ09B0351-0100