SH7265 Datasheet, PDF (1685/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 33 Power-Down Modes
33.2.2 Standby Control Register 2 (STBCR2)
STBCR2 is an 8-bit readable/writable register that controls the operation of individual modules in
power-down modes.
Note: When writing to this register, see section 33.4, Usage Notes.
Bit: 7
6
MSTP
27
-
Initial value: 0
0
R/W: R/W R
5
4
3
2
1
0
-
MSTP MSTP MSTP MSTP
24
23
22
21
-
0
0
0
0
0
0
R R/W R/W R/W R/W R
Initial
Bit Bit Name Value R/W Description
7
MSTP27 0
R/W Module Stop 27
When set to 1, the clock supply to the H-UDI is halted.
0: H-UDI runs.
1: Clock supply to H-UDI is halted.
6, 5 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
4
MSTP24 0
R/W Module Stop 24
When set to 1, the clock supply to FPU0 is halted. After
being set to 1, this bit cannot be cleared by writing 0. This
means that the clock supply the FPU0 cannot be restarted by
clearing this bit to 0. To restart the clock supply to the FPU0,
reset the LSI by a power-on reset.
0: FPU0 runs.
1: Clock supply to FPU0 is halted.
3
MSTP23 0
R/W Module Stop 23
When set to 1, the clock supply to FPU1 is halted. After
being set to 1, this bit cannot be cleared by writing 0. This
means that the clock supply the FPU1 cannot be restarted by
clearing this bit to 0. To restart the clock supply to the FPU1,
reset the LSI by a power-on reset.
0: FPU1 runs.
1: Clock supply to FPU1 is halted.
Rev. 1.00 Mar. 14, 2008 Page 1649 of 1984
REJ09B0351-0100