SH7265 Datasheet, PDF (1690/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 33 Power-Down Modes
Initial
Bit Bit Name Value R/W Description
2
MSTP42 1
R/W Module Stop 42
When set to 1, the clock supply to the SCIF5 is halted.
0: SCIF5 runs.
1: Clock supply to SCIF5 is halted.
1, 0 
All 1 R
Reserved
These bits are always read as 1. The write value should
always be 1.
33.2.5 Standby Control Register 5 (STBCR5)
STBCR5 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes.
Note: When writing to this register, see section 33.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP MSTP MSTP
57 56
55
54
53
52
-
-
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R
R
Initial
Bit
Bit Name Value R/W Description
7
MSTP57 1
R/W Module Stop 57
When set to 1, the clock supply to the IIC3_0 is halted.
0: IIC3_0 runs.
1: Clock supply to IIC3_0 is halted.
6
MSTP56 1
R/W Module Stop 56
When set to 1, the clock supply to the IIC3_1 is halted.
0: IIC3_1 runs.
1: Clock supply to IIC3_1 is halted.
5
MSTP55 1
R/W Module Stop 55
When set to 1, the clock supply to the IIC3_2 is halted.
0: IIC3_2 runs.
1: Clock supply to IIC3_2 is halted.
Rev. 1.00 Mar. 14, 2008 Page 1654 of 1984
REJ09B0351-0100