SH7265 Datasheet, PDF (1501/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 28 2D Graphics Engine (2DG)
(5) Setting of Panel Output
Figure 28.6 shows the relations between the sync signals and the registers setting for display-panel
output. These panel-output settings are made in the following registers.
• MGR_MIXHTMG register: WPH bits and PDPH bits
• MGR_MIXHS register: ALLPH bits and VLDPH bits
• MGR_MIXVTMG register: WPV bits and PDPV bits
• MGR_MIXVS register: ALLPV bits and VLDPV bits
HSync_out
WPH
PDPH
ALLPH
VLDPH
Blended image
(Graphics + moving picture)
display area
Figure 28.6 Relationship between Panel Output and Register Settings
Rev. 1.00 Mar. 14, 2008 Page 1465 of 1984
REJ09B0351-0100