SH7265 Datasheet, PDF (461/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.4 Operation
11.4.1 DMA Transfer Mode
Two DMA transfer modes are available: cycle-stealing transfer mode and pipelined transfer mode.
These modes can be selected by using the DMA transfer mode select bits (MDSEL) of DMA
control register A (DMCNTAn).
Figure 11.3 shows how bus mastership alternates between the DMAC and CPU in DMA transfer
modes.
(1) Cycle-Stealing Transfer Mode
Setting the DMA transfer mode select bits (MDSEL) to 00 selects cycle-stealing transfer mode.
In cycle-stealing transfer mode, the DMAC operates, leaving at least one cycle between the read
and write access cycles (activations) of each single data transfer. For this reason, access from the
CPU is possible during this interval (the CPU can access the BIU part of the source or destination
target).
(2) Piepelined Transfer Mode
Setting the DMA transfer mode select bits (MDSEL) to 01 selects pipelined transfer mode.
In pipelined transfer mode, the DMAC consecutively accesses the bus for read access or write
access or both. For this reason, access from the CPU is not accepted till the current single operand
transfer ends (the CPU cannot access the BIU part of the source or destination target).
Piepelined transfer through a single BIU is also not possible.
Rev. 1.00 Mar. 14, 2008 Page 425 of 1984
REJ09B0351-0100