SH7265 Datasheet, PDF (1257/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Bit
3 to 0
Bit Name
UTST[3:0]
Section 25 USB 2.0 Host/Function Module (USB)
Initial
Value R/W Description
0000
R/W • When the host controller function is selected
These bits can be set after writing 1 to DRPD for the
target port, either PORT0 or PORT1, to be tested.
These bits are common to PORT0 and PORT1. This
module outputs waveforms to the USB port for which
both DPRD and UACT have been set to 1. This
module also performs high-speed termination for
PORT0 and PORT1 by writing to these bits.
Procedure for setting the UTST bits:
1. Power-on reset the system.
2. Start the clock supply (set SCKE to 1).
3. Set DCFM and DPRD to 1 (setting HSE to 1 is
not required).
4. Set USBE to 1.
5. Set the UTST bits to the appropriate value
according to the test specifications.
6. Set the UACT bit for the target port to 1.
Procedure for modifying the UTST bits:
1. In the state after step 6 above, clear UACT
and USBE to 0.
2. Set USBE to 1.
3. Set the UTST bits to the appropriate value
according to the test specifications.
4. Set the UACT bit for the target port to 1.
Note: When these bits are set to Test_SE0_NAK
(1011), this module does not output the SOF
packet even for the port for which UACT is set
to 1. When these bits are set to
Test_Force_Enable (1101), this module
outputs the SOF packet to the port for which
UACT is set to 1. In this test mode, this module
does not perform the pertinent control even
when a high-speed disconnection is detected
(detection of the DTCH interrupt).
When setting the UTST bits, the PID bits for all
the pipes should be set to NAK.
To return to normal USB communication after a
test mode has been set and executed, perform
a power-on reset.
Rev. 1.00 Mar. 14, 2008 Page 1221 of 1984
REJ09B0351-0100