SH7265 Datasheet, PDF (1318/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
Initial
Value R/W Description
6 to 0 MXPS[6:0]
H'40
R/W Maximum Packet Size∗
Specify the maximum packet size for the DCP.
Note: Do not set values that do not conform to the
USB Specification.
While MXPS is 0, do not write to the FIFO
buffer or do not set PID to BUF.
Note: ∗ The DEVSEL bit should be set while CSSTS is 0, PID is NAK, and SUREQ is 0.
The MXPS bit should be set while CSSTS is 0 and PID is NAK.
Before modifying these bits after modifying the PID bits for the DCP from BUF to NAK,
check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to
NAK by this module, checking PBUSY is not necessary.
When the function controller function is selected, the DEVSEL bit should be set to 0.
25.3.34 DCP Control Register (DCPCTR)
DCPCTR is a register that is used to confirm the buffer memory status, control setup transactions
and split transactions, change and confirm the data PID sequence bit, and set the response PID for
the DCP.
This register is initialized by a power-on reset. The CCPL and PID[2:0] bits are initialized by a
USB bus reset.
Bit: 15 14 13 12 11 10
BSTS
SUREQ CSCLR
CSSTS
SUREQ
CLR
—
Initial value: 0
0
0
0
0
-
R/W: R R/W*² R*¹/ R
W*²
R*¹/ R
W*²
Notes: 1. This bit is always read as 0.
2. Only 1 can be written to.
9
8
7
6
5
4
3
2
1
0
— SQCLR SQSET SQMON PBUSY PINGE — CCPL
PID[1:0]
-
0
0
1
R R*¹/ R*¹/ R
W*² W*²
0
0
-
0
0
0
R R/W R R/W R/W R/W
Rev. 1.00 Mar. 14, 2008 Page 1282 of 1984
REJ09B0351-0100