SH7265 Datasheet, PDF (944/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
19.3.7 FIFO Data Register (SSIFDR)
In transmission, SSIFDR operates as a FIFO register consisting of eight stages of 32-bit registers
for storing data to be serially transmitted. On detecting that the transmit data register (SSITDR) is
empty, the SSIF transfers the data for transmission written to SSIFDR to SSITDR to start serial
transmission, which can continue until SSIFDR becomes empty. SSIFDR can be written to by the
CPU at any time. Note that when SSIFDR is full of data (32 bytes), the next data cannot be written
to it and will be ignored if writing is attempted.
In reception, SSIFDR operates as a FIFO register consisting of eight stages of 32-bit registers for
storing serially received data. When four bytes of data have been received, the SSIF transfers the
received data in the receive data register (SSIRDR) to SSIFDR to complete reception operation.
Reception can continue until 32 bytes of data have been stored to SSIFDR. SSIFDR can be read
by the CPU but cannot be written to. Note that when SSIFDR is read when it stores no received
data, undefined values will be read. After SSIFDR becomes full of received data, the data received
thereafter will be lost.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * Not writable during reception.
Rev. 1.00 Mar. 14, 2008 Page 908 of 1984
REJ09B0351-0100