SH7265 Datasheet, PDF (466/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
Table 11.10 shows the combinations of DMA transfer modes and DMA transfer conditions.
Table 11.10 Combinations of DMA Transfer Modes and DMA Transfer Conditions
DMA Transfer Condition
Unit Operand
Transfer
DSEL = 00
Sequential Operand
Transfer
DSEL = 01
Non-Stop Transfer
DSEL = 11
Transfer Cycle-Stealing OK
OK
OK
Mode Transfer
(between any two BIUs (between any two BIUs (between any two BIUs
MDSEL = 00 and the same BIU)
and the same BIU)
and the same BIU)
Piepelined
transfer
MDSEL = 01
OK
(between two different
BIUs*²)
OK
(between two different
BIUs*²)
Partly OK*¹
(between two different
BIUs, excluding
BIU_EIU*²)
Notes: 1. Non-stop transfer to BIU_E in pipelined transfer mode cannot be set.
2. Piepelined transfer to the same BIU is prohibited.
11.4.3 DMA Activation
(1) Initial setting of DMAC
Make the initial setting of each register before setting the DMA transfer enable bit (DEN) to 1.
Once data transfer has been started, these settings cannot be changed.
The following shows an example of DMAC initial setting.
1. DMA mode register (DMMODn)
2. DMA control register A (DMCNTAn)
3. DMA control register B (DMCNTBn)
4. DMA current source address register (DMCSADRn)
5. DMA reload source address register (DMRSADRn)
 When the reload function is used
6. DMA current destination address register (DMCDADRn)
7. DMA reload destination address register (DMRDADRn)
 When the reload function is used
8. DMA current byte count register (DMCBCTn)
9. DMA reload byte count register (DMRBCTn)
 When the reload function is used
Rev. 1.00 Mar. 14, 2008 Page 430 of 1984
REJ09B0351-0100