SH7265 Datasheet, PDF (1562/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 28 2D Graphics Engine (2DG)
• Items calculated by the user
Fractional part of the result of calculating the vertical delta (VDLT_DCML)
Cv is calculated for use in obtaining VDLT_DCML.
Cv = INT (SV/DV) × 4096 = INT (100/150) × 4096) = 2730.
Since VDLT_DCML becomes the lower-order 12 bits of Cv, VDLT_DCML = 2730.
When the line number (SL) is 78, use the formula given earlier to discern whether duplicate-line
settings are or are not necessary.
b0 = INT (2730 × INT (78 × 150/100) + 1365 + (2730 × (−2)))/4096 = 76
b1 = INT (2730 × INT (78 × 150/100) + 1365 + (2730 × (−1)))/4096 = 77
b2 = INT (2730 × INT (78 × 150/100) + 1365 + (2730 × (0)))/4096 = 78
b3 = INT (2730 × INT (78 × 150/100) + 1365 + (2730 × (1)))/4096 = 78
IF (OR (AND (77 = (78 – 1), 77 = 76),
AND (77 = (78 – 1), 77 = 78),
AND (78 = (78 – 1), 78 = 78)), 2, 1)
Since all terms of the conditional expression are false, the transfer of line 78 is only to proceed
once.
[Example of settings for pixel-data transfer]
As an example, the text below explains Example 1 in table 28.10.
In this case, make settings such that pixel data (in line units) is transferred from the CPU to the
2DG module in the following order.
Data for transfer (in line units) = 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, …
In this way, lines 1, 3, 5, 7 etc. of pixel data (in line units) must each be transferred twice
consecutively.
Rev. 1.00 Mar. 14, 2008 Page 1526 of 1984
REJ09B0351-0100