SH7265 Datasheet, PDF (347/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus State Controller (BSC)
3. Tend (First Wait End Cycle)
This is the final cycle in the first series of read cycle wait or write cycle wait cycles. In write
access, the second and subsequent page accesses start from the next cycle, unless a write data
output delay cycle has been specified (with a value other than 0). The RD, WEn, or WE signal
is negated (high level) in the next cycle if the RD assert wait or WR assert wait setting is other
than 0. If the RD assert wait or WR assert wait setting is 0, the RD, WEn, or WE signal
continues to be asserted (low level). The CSn signal is not negated and continues to be asserted
(low level). The RD_WR signal operates with the same timing as for the CSn signal. In page
read access, the succeeding bus access starts without waiting for the read data sample cycle
(Trd).
4. Tdw1 to Tdwn (Write Data Output Delay Cycle)
In write access, write data output delay cycles are inserted between the wait end cycle and the
following page access if the write data output delay wait setting is other than 0. Assertion of
the address and output data is extended for the duration of this interval. Also, the WEn and WE
signals are negated (high level).
5. Tpw1 to Tpwn (Page Read Cycle Wait, Page Write Cycle Wait)
For the second and subsequent bus cycles in a page access, the page read cycle wait and page
write cycle wait settings are used in place of the read cycle wait and write cycle wait settings.
The WR assert wait setting works in the same way as for the first bus cycle. The RD assert
wait setting operates differently depending on the page read access mode (PRMOD) setting
value.
PRMOD = 0: RD assert wait setting operates in the same way as for the first bus cycle.
PRMOD = 1: RD assert wait setting is invalid.
Operation is the same as for RD assert wait setting of 0.
6. Tend/Tdw1 to Tdwn (Wait End Cycle/Write Data Output Delay Cycle)
The operation is the same as for the first access (3 and 4 above).
7. Tn1 to Tnm (CS Delay Cycle)
These are the cycles between the final wait end cycle and when CSn is negated (high level).
The number of CS delay cycles is counted beginning from the wait end cycle.
8. Trd (Final Read Data Sample Cycle)
This is the final sample cycle for read data.
Rev. 1.00 Mar. 14, 2008 Page 311 of 1984
REJ09B0351-0100