SH7265 Datasheet, PDF (15/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

11.3.2 DMA Current Destination Address Registers (DMCDADRn)......................... 379
11.3.3 DMA Current Byte Count Register (DMCBCTn) ............................................ 380
11.3.4 DMA Reload Source Address Register (DMRSADRn) ................................... 382
11.3.5 DMA Reload Destination Address Register (DMRDADRn) ........................... 383
11.3.6 DMA Reload Byte Count Register (DMRBCTn) ............................................. 384
11.3.7 DMA Mode Register (DMMODn) ................................................................... 385
11.3.8 DMA Control Register A (DMCNTAn) ........................................................... 394
11.3.9 DMA Control Register B (DMCNTBn) ........................................................... 401
11.3.10 DMA Activation Control Register (DMSCNT)................................................ 405
11.3.11 DMA Interrupt Control Register (DMICNT) ................................................... 406
11.3.12 DMA Common Interrupt Control Register (DMICNTA)................................. 407
11.3.13 DMA Interrupt Status Register (DMISTS) ....................................................... 408
11.3.14 DMA Transfer End Detection Register (DMEDET) ........................................ 409
11.3.15 DMA Arbitration Status Register (DMASTS).................................................. 411
11.3.16 DMA Two-Dimensional Addressing Column Setting Register
(DM2DCLMm)................................................................................................. 412
11.3.17 DMA Two-Dimensional Addressing Row Setting Register
(DM2DROWm) ................................................................................................ 414
11.3.18 DMA Two-Dimensional Addressing Block Setting Register
(DM2DBLKm).................................................................................................. 415
11.3.19 DMA Two-Dimensional Addressing Next Row Offset Register
(DM2DNROSTm) ............................................................................................ 416
11.3.20 DMA Two-Dimensional Addressing Next Block Offset Register
(DM2DNBOSTm) ............................................................................................ 417
11.3.21 DMA Two-Dimensional Addressing Next Line Offset Register
(DM2DNLOSTm)............................................................................................. 418
11.3.22 DMA Reload Two-Dimensional Addressing Column Setting Register
(DMR2DCLMm) .............................................................................................. 419
11.3.23 DMA Reload Two-Dimensional Addressing Row Setting Register
(DMR2DROWm).............................................................................................. 420
11.3.24 DMA Reload Two-Dimensional Addressing Block Setting Register
(DMR2DBLKm)............................................................................................... 421
11.3.25 DMA Reload Two-Dimensional Addressing Next Row Offset Register
(DMR2DNROSTm).......................................................................................... 422
11.3.26 DMA Reload Two-Dimensional Addressing Next Block Offset Register
(DMR2DNBOSTm).......................................................................................... 423
11.3.27 DMA Reload Two-Dimensional Addressing Next Line Offset Register
(DMR2DNLOSTm) .......................................................................................... 424
11.4 Operation .......................................................................................................................... 425
11.4.1 DMA Transfer Mode ........................................................................................ 425
Rev. 1.00 Mar. 14, 2008 Page xv of xxxvi