SH7265 Datasheet, PDF (1491/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 28 2D Graphics Engine (2DG)
28.3.27 Panel-Output Vertical Timing Setting Register for Output-Block
(MGR_MIXVTMG)
The register MGR_MIXVTMG sets the vertical timing of signal output to the panel. The register
value is applied in synchronization with the VSYNC signal. For details, see section 28.4.1 (5),
Setting of Panel Output.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10
WPV
-
-
Initial value: 0
0
1
1
-
-
R/W: R/W R/W R/W R/W R
R
9
8
7
6
5
4
3
2
1
0
-
PDPV
-
0
0
0
0
0
0
1
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit name
31 to 16 
15 to 12 WPV
11 to 9 
8 to 0 PDPV
Initial
Value
R/W
Undefined R
0011
R/W
Undefined R
H'004
R/W
Description
Reserved
The read value is undefined. The write value should
always be 0.
Panel Output VSYNC Pulse Width
These bits set the pulse width of VSYNC for panel
output using the number of lines from the falling edge
of VSync_out.
Valid range: 1 to 15 lines
Reserved
The read value is undefined. The write value should
always be 0.
Panel Output Image Vertical Reading Start Timing
These bits set the start timing to read image to be
output to the panel in the vertical direction using the
number of lines from the rising edge of VSync_out.
Valid range: 0 to 511 lines
Rev. 1.00 Mar. 14, 2008 Page 1455 of 1984
REJ09B0351-0100