SH7265 Datasheet, PDF (77/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 1 Overview
Classification
Controller area
network
(RCAN-TL1)
Symbol
CTx1, CTx0
CRx1, CRx0
IEBus^TM
controller (IEB)
A/D converter
(ADC)
IETxD
IERxD
AN7 to AN0
ADTRG
D/A converter
(DAC)
Common to
analog circuits
DA1, DA0
AVcc
AVss
AVref
AND/NAND
flash memory
controller
(FLCTL)
FOE
FSC
FCE
FCDE
I/O Name
Function
O CAN bus transmit Output pin for transmit data on the
data
CAN bus.
I
CAN bus receive Output pin for receive data on the
data
CAN bus.
O IEB transmit data Output pin for transmit data on IEB.
I
IEB receive data Input pin for receive data on IEB.
I
Analog input pins Analog input pins.
I
A/D conversion External trigger input pin for starting
trigger input
A/D conversion.
O Analog output Analog output pins.
pins
I
Analog power Power supply pins for the A/D
supply
converter and D/A converter.
I
Analog ground Ground pins for the A/D converter
and D/A converter.
I
Analog reference Analog reference voltage pins for the
voltage
A/D converter and D/A converter.
O Flash memory Address latch enable: Asserted for
output enable address output and negated for data
I/O.
Output enable: Asserted for data
input or status read.
O Flash memory Read enable: Data is read on the
serial clock
falling edge of this signal.
Serial clock: Data is inputs/output in
synchronization with this signal.
O Flash memory Chip enable: Enables the flash
chip enable
memory connected to this LSI.
O Flash memory Command latch enable: Asserted at
command data command output.
enable
Command data enable: Asserted at
command output.
Rev. 1.00 Mar. 14, 2008 Page 41 of 1984
REJ09B0351-0100