SH7265 Datasheet, PDF (1419/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 AT Attachment Packet Interface (ATAPI)
IDEIORD#/
IDEIOWR#
DCT
ATA
Address
DST
DPW
DST
DCT: Period setting
DPW: Low-level width setting for the IDEIORD#/IDEIOWR# pulse
DST: Setup time setting for address and IDEIORD#/IDEIOWR#
Note: The DCT, DPW, and DST are determined by their respective register settings × enhanced bus clock period.
Figure 27.2 PIO Timing Register
• PIO timing register value table (master/slave)
Enhanced Bus
Clock
66 MHz
Mode 0
H'29A5
Mode 1
H'1BA4
Mode 2
H'11A3
Mode 3
H'0D3B
Mode 4
H'0933
Rev. 1.00 Mar. 14, 2008 Page 1383 of 1984
REJ09B0351-0100