SH7265 Datasheet, PDF (934/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
Initial
Bit
Bit Name Value R/W Description
26
OIRQ
0
R/(W)* Overflow Error Interrupt Status Flag
This status flag indicates that data was supplied at a
higher rate than was required.
In either case this bit is set to 1 regardless of the value
of the OIEN bit and can be cleared by writing 0 to this
bit.
If OIRQ = 1 and OIEN = 1, an interrupt occurs.
• TRMD = 0 (Receive mode)
If OIRQ = 1, SSIRDR was not read before there
was new unread data written to it. This will lead to
the loss of a sample and a potential corruption of
multi-channel data.
Note: When overflow error occurs, the current data in
the data buffer of this module is overwritten by
the next incoming data from the SSI interface.
• TRMD = 1 (Transmit mode)
If OIRQ = 1, SSITDR had data written to it while the
FIFO is full (DC = H’8). This will lead to the loss of a
sample and a potential corruption of multi-channel
data.
25
IIRQ
1
R
Idle Mode Interrupt Status Flag
This interrupt status flag indicates whether the SSIF
module is in idle state.
This bit is set regardless of the value of the IIEN bit to
allow polling.
The interrupt can be masked by clearing IIEN, but
cannot be cleared by writing to this bit.
If IIRQ = 1 and IIEN = 1, an interrupt occurs.
0: The SSIF module is not in idle state.
1: The SSIF module is in idle state.
Rev. 1.00 Mar. 14, 2008 Page 898 of 1984
REJ09B0351-0100