SH7265 Datasheet, PDF (1698/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 33 Power-Down Modes
33.2.10 System Control Register 3 (SYSCR3)
SYSCR3 is an 8-bit readable/writable register that enables or disables access (read/write) from
CPU1 to each page of the high-speed on-chip RAM0. Other descriptions on this register are the
same as SYSCR1.
Note: When writing to this register, see section 33.4, Usage Notes.
33.2.11 System Control Register 4 (SYSCR4)
SYSCR4 is an 8-bit readable/writable register that enables or disables writing from CPU1 to each
page of the high-speed on-chip RAM0. Other descriptions on this register are the same as
SYSCR2.
Note: When writing to this register, see section 33.4, Usage Notes.
33.2.12 System Control Register 5 (SYSCR5)
SYSCR5 is an 8-bit readable/writable register that enables or disables access (read/write) from the
DMAC to each page of the high-speed on-chip RAM0. Other descriptions on this register are the
same as SYSCR1.
Note: When writing to this register, see section 33.4, Usage Notes.
33.2.13 System Control Register 6 (SYSCR6)
SYSCR6 is an 8-bit readable/writable register that enables or disables writing from the DMAC to
each page of the high-speed on-chip RAM0. Other descriptions on this register are the same as
SYSCR2.
Note: When writing to this register, see section 33.4, Usage Notes.
Rev. 1.00 Mar. 14, 2008 Page 1662 of 1984
REJ09B0351-0100