SH7265 Datasheet, PDF (1571/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 28 2D Graphics Engine (2DG)
28.4.5 Interrupts
2DG interrupt signals are classified into two types: the interrupts related to the blitter (BLT
interrupts) and the interrupts related to the output block (output interrupts). Table 28.12 shows the
interrupt sources and the conditions on which each source is generated and can be cleared. Figure
28.56 shows the structure of the interrupts.
Table 28.12 Interrupt Sources and Corresponding Generation/Clearing Conditions
Interrupt Sources Status Bit
Generation Conditions Clearing Conditions
BLT interrupts
DC buffer full flag
(IRQ_DHFUL bit)
The DC buffer becomes This bit is cleared when 1 is
full.
written to the DIS_DHFUL bit
in GR_INTDIS.
SA buffer full flag
(IRQ_ASHFUL bit)
The SA buffer becomes This bit is cleared when 1 is
full.
written to the DIS_ASHFUL
bit in GR_INTDIS.
SB buffer full flag
(IRQ_SHFUL bit)
The SB buffer becomes This bit is cleared when 1 is
full.
written to the DIS_SHFUL bit
in GR_INTDIS.
Blit operation
completed
(INT_GR bit)
Blitter operation is
completed.
This bit is cleared when 1 is
written to the DIS_GR bit in
GR_INTDIS.
Output interrupts SE buffer full flag
(IRQ_DEMPT bit)
The SE buffer becomes
full.
This bit is cleared when 1 is
written to the DIS_DEMPT bit
in GR_INTDIS.
VSYNC input for
output block
(INT_VSYC bit)
VSYNC input is supplied. This bit is cleared when 1 is
(when display is on.) written to the DIS_VSYC bit in
GR_INTDIS.
Output underflow for Underflow of output from This bit is cleared when 1 is
output block
the output block occurs. written to the DIS_UDFL bit in
(INT_UDFL bit)
GR_INTDIS.
Last line captured by The last line is captured This bit is cleared when 1 is
output block
in the SE buffer.
written to the DIS_FILD bit in
(INT_FILD bit)
GR_INTDIS.
Rev. 1.00 Mar. 14, 2008 Page 1535 of 1984
REJ09B0351-0100