SH7265 Datasheet, PDF (329/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus State Controller (BSC)
10.4.11 SDRAM Power-Down Control Register (SDPWDCNT)
SDPWDCNT controls transition to and recovery from power-down mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- DPWD
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Bit
31 to 1
Initial
Bit Name Value

All 0
0
DPWD 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W SDRAM Common Power-Down Enable
This bit controls transition to and recovery from power-
down mode for all channels simultaneously. Setting
DPWD to 1 causes all channels to transfer to power-down
mode. Clearing DPWD to 0 causes all channels to recover
from power-down mode. If an auto-refresh is in progress,
the transition to power-down mode is delayed until the
auto-refresh completes.
0: Power-down disabled
1: Power-down enabled
Rev. 1.00 Mar. 14, 2008 Page 293 of 1984
REJ09B0351-0100