SH7265 Datasheet, PDF (179/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Exception Handling
6.2 Resets
6.2.1 Input/Output Pins
Table 6.5 shows the reset-related pin configuration.
Table 6.5 Pin Configuration
Pin Name
Power-on reset
Symbol
RES
Manual reset
MRES
I/O
Input
Input
Function
When this pin is driven low, this LSI shifts to
the power-on reset processing.
When this pin is driven low, this LSI shifts to
the manual reset processing.
6.2.2 Types of Reset
A reset is the highest-priority exception source. There are two kinds of reset, power-on and
manual. As shown in table 6.6, the CPU state is initialized in both a power-on reset and a manual
reset. On-chip peripheral module registers are also initialized by a power-on reset, but not by a
manual reset.
Table 6.6 Timing of Exception Source Detection and Start of Exception Handling
Conditions for Transition to Reset State
Internal States
Type
RES or
MRES H-UDI command
WDT0 WDT1
overflow overflow CPU
On-chip WRCSR of
peripheral WDT0 and
module, WDT1,
I/O port FRQCR of CPG
Power-on Low 


reset
High H-UDI reset assert


command is set
Initialized Initialized Initialized
Initialized Initialized Initialized
High
Command other than Power-on Power-on Initialized Initialized Not
H-UDI reset assert is set reset
reset
initialized
Manual Low Command other than 

reset
H-UDI reset assert is set
Initialized Not
Not
initialized* initialized
High
Command other than Manual Manual
H-UDI reset assert is set reset
reset
Initialized Not
Not
initialized* initialized
Note: * However, the BN3 to BN0 bits of IBNR of the INTC are initialized.
Rev. 1.00 Mar. 14, 2008 Page 143 of 1984
REJ09B0351-0100