SH7265 Datasheet, PDF (480/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.7.3 Sense Mode for DMA Requests
If the DREQ0 to DREQ3 pins (DCTG = 000001 to 000100) are selected by the DMA request
source select bits (DCTG), a level sense (01 or 11) or an edge sense (00 or 10) can be selected
from the input sense mode select bits (STRG) of DMA control register A (DMCNTAn).
If the software trigger (DCTG = 000000) is selected as the DMA request source, select the rising-
edge sense (00). If the DMA request from the on-chip peripheral modules (DCTG = 000101 to
111001) is selected as the DMA request source, set the sense mode show in table 11.8.
The following describes the level sense and edge sense.
(1) Level Sense
If a level sense (STRG = 01 or 11) is selected, whether a DMA request is present is judged from
the DMA request signal level. A DMA request is not retained in the DMAC, so retain the DMA
request signal level till the acceptance of the DMA request is confirmed.
Figure 11.8 is an example of DMA request acceptance processing when a level sense is selected.
CKIO
DMAC state
(internal state)
DREQ0 to DREQ3
(low level sense)
DACK0 to DACK3
DMA request bit
Start of single operand transfer
Read
Hold the DMA request signal until DMA acknowledge
output goes active to indicate the acceptance of the request.
Write
[Legend]
: Sampling point for DMA request signal
Figure 11.8 Example of DMA Request Acceptance Processing When a Level Sense Is
Selected
Rev. 1.00 Mar. 14, 2008 Page 444 of 1984
REJ09B0351-0100