SH7265 Datasheet, PDF (735/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 14 Watchdog Timer (WDT)
Reset input
Reset signal to
entire system
RES
WDTOVF
Figure 14.6 Example of System Reset Circuit Using WDTOVF Signal
14.5.5 Manual Reset in Watchdog Timer Mode
When a manual reset occurs in watchdog timer mode, the bus cycle is continued. If a manual reset
occurs during burst transfer by the DMAC, manual reset exception handling will be pended until
the CPU acquires the bus mastership.
14.5.6 Transition to Deep Standby Mode
The WDT does not directly perform transition to or release of deep standby mode. However, since
the WDT may generate a watchdog timer reset or interval timer interrupt during transition to deep
standby mode by CPU0 issuing the SLEEP instruction, clear the WTCSR0.TME and
WTCSR1.TME bits to 0 to stop the WDT before issuance of the SLEEP instruction.
Rev. 1.00 Mar. 14, 2008 Page 699 of 1984
REJ09B0351-0100