SH7265 Datasheet, PDF (11/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Exception Handling ...........................................................................137
6.1 Overview........................................................................................................................... 137
6.1.1 Types of Exception Handling and Priority........................................................ 137
6.1.2 Exception Handling Operations ........................................................................ 139
6.1.3 Exception Handling Vector Table..................................................................... 141
6.2 Resets................................................................................................................................ 143
6.2.1 Input/Output Pins.............................................................................................. 143
6.2.2 Types of Reset .................................................................................................. 143
6.2.3 Power-On Reset ................................................................................................ 144
6.2.4 Manual Reset .................................................................................................... 146
6.3 Address Errors .................................................................................................................. 147
6.3.1 Address Error Sources ...................................................................................... 147
6.3.2 Address Error Exception Handling ................................................................... 148
6.4 Register Bank Errors......................................................................................................... 149
6.4.1 Register Bank Error Sources............................................................................. 149
6.4.2 Register Bank Error Exception Handling ......................................................... 149
6.5 Sleep Errors ...................................................................................................................... 150
6.5.1 Sleep Error Source ............................................................................................ 150
6.5.2 Sleep Error Exception Handling ....................................................................... 150
6.6 Interrupts........................................................................................................................... 151
6.6.1 Interrupt Sources............................................................................................... 151
6.6.2 Interrupt Priority Level ..................................................................................... 151
6.6.3 Interrupt Exception Handling ........................................................................... 152
6.7 Exceptions Triggered by Instructions ............................................................................... 153
6.7.1 Types of Exceptions Triggered by Instructions ................................................ 153
6.7.2 Trap Instruction................................................................................................. 154
6.7.3 Slot Illegal Instructions ..................................................................................... 154
6.7.4 General Illegal Instructions............................................................................... 154
6.7.5 Integer Division Exceptions.............................................................................. 155
6.7.6 FPU Exceptions ................................................................................................ 155
6.8 When Exception Sources Are Not Accepted .................................................................... 157
6.9 Stack Status after Exception Handling Ends..................................................................... 158
6.10 Usage Notes ...................................................................................................................... 160
6.10.1 Value of Stack Pointer (SP) .............................................................................. 160
6.10.2 Value of Vector Base Register (VBR) .............................................................. 160
6.10.3 Address Errors Caused by Stacking of Address Error Exception Handling ..... 160
Section 7 Interrupt Controller (INTC) ...............................................................161
7.1 Features............................................................................................................................. 161
7.2 Input/Output Pins.............................................................................................................. 163
Rev. 1.00 Mar. 14, 2008 Page xi of xxxvi