SH7265 Datasheet, PDF (1197/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
0
TRINTE0 0
R/W FLDTFIFO Transfer Request Enable to CPU
Enables or disables an interrupt request to the CPU by
a transfer request issued from FLDTFIFO.
0: Disables an interrupt request to the CPU by a
transfer request from FLDTFIFO
1: Enables an interrupt request to the CPU by a transfer
request from FLDTFIFO
When the DMA transfer is enabled, this bit should be
cleared to 0.
Note: * Only 0 can be written to these bits.
Rev. 1.00 Mar. 14, 2008 Page 1161 of 1984
REJ09B0351-0100