SH7265 Datasheet, PDF (1360/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name Value R/W Description
8
TRCLR
0
R*¹/W*² Transaction Counter Clear*³
Setting this bit to 1 clears the transaction counter to
0.
0: No effect
1: The current counter is cleared.
7 to 0 
Undefined R
Reserved
Undefined values are read from these bits. The write
value should always be 0.
Notes: 1. Only 0 can be read.
2. Only 1 can be written to.
3. Modify each bit when CSSTS = 0 and PID = NAK.
Before modifying these bits after modifying the PID bits for the selected pipe from BUF
to NAK, make sure that CSSTS = 0 and PBUSY = 0. However, if the PID bits have
been modified to NAK by this module, checking of PBUSY is not necessary.
25.3.43 Transaction Counter Registers (PIPEnTRN) (n = 1 to 5)
The PIPEnTRN registers are used to specify the number of transactions by DMA transfer for
PIPE1 to PIPE5, and the current number of transactions can be read from them.
These registers are initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TRNCNT[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Mar. 14, 2008 Page 1324 of 1984
REJ09B0351-0100