SH7265 Datasheet, PDF (245/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 Interrupt Controller (INTC)
* Interrupt requests that are set for edge-detection are held pending until they are
accepted. IRQ interrupts, however, can be cancelled by accessing the IRQ interrupt
request registers (C0IRQRR and C1IRQRR). For details, see section 7.4.4, IRQ
Interrupts.
Interrupts held pending due to edge-detection are cleared by a power-on reset.
Program
execution state
Interrupt?
Yes
NMI?
Yes
No
No
User break?
Yes
Read exception
handling vector table
Save SR to stack
Copy interrupt
level to I3 to I0
Save PC to stack
Branch to exception
service routine
No
H-UDI
No
interrupt?
Yes
No
Level 15
interrupt?
Yes
Yes
I3 to I0 ≤
level 14?
No
Level 14
No
interrupt?
Yes
Level 1
No
interrupt?
I3 to I0 ≤
Yes
level 13?
No _Yes
I3 to I0 =
level 0?
No
Figure 7.2 Interrupt Operation Flow
Rev. 1.00 Mar. 14, 2008 Page 209 of 1984
REJ09B0351-0100