SH7265 Datasheet, PDF (1606/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 29 AESOP
29.4.8 DMA Transfer (DMA for data input transfer to AESOP)
Since data input transfer DMA is set in the data transfer mode setting, 1024 times of requests are
generated because one frame of data is continuously requested each time the data request
condition occurs.
Details of data transfer should be set using DMAC registers.
29.4.9 DMA Transfer (DMA for data output transfer to AESOP)
Since data output transfer DMA is set in the data transfer mode setting, 1024 times of requests are
generated each time4 Kbytes of data are stored in the DOUT_RAM. Before 4 Kbytes of data are
stored in the DOUT_RAM, several frames of encoding processing are executed.
If the DOUT_RAM holds data less than 4 Kbytes when encoding processing of input data for the
final frame is complete, the data should be forcibly transferred by register setting. At this time, the
amount of data to be transferred can be confirmed by SDBTR.
29.4.10 Processing Status End Interrupt Processing
In the processing status end interrupt processing, the data is transferred if AESOP interrupt source
is set after input PCM data of the final frame has been transferred and the DOUT_RAM holds data
less than 4 Kbytes when encoding processing is complete.
The following describes two types of processing procedures (when a timer interrupt is used and
not used). In either processing procedure, the amount of input PCM data should be managed by
the host CPU to determine the end of input PCM data transfer.
Rev. 1.00 Mar. 14, 2008 Page 1570 of 1984
REJ09B0351-0100