SH7265 Datasheet, PDF (256/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 Interrupt Controller (INTC)
7.9.2 Save and Restore Operations after Saving to All Banks
If the CPU accepts an interrupt and the use of the register banks is enabled for that interrupt when
saving to all register banks has been performed, automatic saving to the stack is performed instead
of register bank saving if the BOVE bits in the bank number registers (C0IBNR and C1IBNR) are
cleared to 0. If the BOVE bits in C0IBNR and C1IBNR are set to 1, a register bank overflow
exception occurs and data is not saved to the stack.
Saving to the stack and restoration from the stack take place as described below:
(1) Saving to Stack
1. The status register (SR) and program counter (PC) are saved to the stack during interrupt
exception handling.
2. The values in the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are saved to the
stack. The register values are saved to the stack in the order of MACL, MACH, GBR, PR,
R14, R13, …, R1, and R0.
3. The register bank overflow bit (BO) in the SR is set to 1.
4. The bank number bits (BN) in the bank number registers (C0IBNR and C1IBNR) remain set to
the maximum value of 15.
(2) Restoration from Stack
When the RESBANK (restore from register bank) instruction is executed with the register bank
overflow bit (BO) in the SR set to 1, the following operation is performed:
1. The values in the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored
from the stack. The register values are restored from the stack in the order of R0, R1, …, R13,
R14, PR, GBR, MACH, and MACL.
2. The bank number bits (BN) in the bank number registers (C0IBNR and C1IBNR) remain set to
the maximum value of 15.
Rev. 1.00 Mar. 14, 2008 Page 220 of 1984
REJ09B0351-0100