SH7265 Datasheet, PDF (369/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus State Controller (BSC)
(12) SDRAMC Setting Examples
The SDRAMC setting procedure, timing register setting examples, and the procedure for
transitioning to and recovering from self-refresh mode, power-down mode, and deep-power-down
mode are described below.
(a) SDRAMC Setting Procedure
Figure 10.25 shows the SDRAMC setting procedure.
Note that the specifications such as the power-up sequence may vary with the SDRAM in use.
Study the SDRAM specifications carefully before designing your system. For example, when the
SDRAM in use requires that the DQM pin be held "H" during the initialization sequence, set the
SDRAM according to the procedure shown in figure 10.25 (b). Since the initialization sequence
adopted for this LSI is compliant with the JEDEC standard, the value of DQM pin is not
guaranteed from the power-up is supplied and through the initialization sequence.
Rev. 1.00 Mar. 14, 2008 Page 333 of 1984
REJ09B0351-0100