SH7265 Datasheet, PDF (1426/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 AT Attachment Packet Interface (ATAPI)
(10) ATAPI signal status register (ATAPI_SIG_ST)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
- DDMARDY DMARQ
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
31 to 2
1
Initial
Bit Name Value


DDMARDY 
0
DMARQ 
R/W Description
R
Reserved
R
This bit indicates the state of the ATAPIDDMARDY
(inversion of IDEIORDY) signal.
R
This bit indicates the state of the ATAPIDMARQ
(IDEDREQ) signal.
(11) Byte swap register (ATAPI_BYTE_SWAP)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BYTE
SWAP
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Bit
31 to 1
0
Bit Name
Initial
Value


BYTESWAP 0
R/W
R
R/W
Description
Reserved
This bit controls whether to swap the upper eight bits
with the lower eight bits on the ATAPI interface.
1: Byte swap is executed between the APAPI interface
and enhanced bus.
Byte swap is enabled only if bit 0 in the ATAPI control
register is 1 and DMA mode has initiated.
Rev. 1.00 Mar. 14, 2008 Page 1390 of 1984
REJ09B0351-0100