SH7265 Datasheet, PDF (1618/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 30 Pin Function Controller (PFC)
Table 30.6 Multiplexed Pins (Port F)
0000
Setting
Register
Function 1
(General I/O)
PFCRL2 PF4 I/O (port)
PFCRL1 PF3 I/O (port)
PF2 I/O (port)
PF1 I/O (port)
PF0 I/O (port)
Setting of Mode Bits (PFnMD[3:0])
0001
0010
0011
0100
0101
Function 2
(Related Module)
Function 3
(Related Module)
Function 4
(Related Module)
Function 5
(Related Module)
Function 6
(Related Module)

DACK3 output
CTx1 output
CTx0&CTx1 output DACT3 output
(DMAC)
(RCAN-TL1)
(RCAN-TL1)
(DMAC)

DREQ3 input
CRx1 input
CRx0/CRx1 input 
(DMAC)
(RCAN-TL1)
(RCAN-TL1)


CTx0 output
IETxD output (IEB) 
(RCAN-TL1)

SDA3 I/O (IIC3)
CRx0 input
IERxD input (IEB) 
(RCAN-TL1)

SCL3 I/O (IIC3)



Table 30.7 Multiplexed Pins (Port G)
0000
Setting Function 1
Register (General I/O)
PGCRL2 PG7 input (port)
PG6 input (port)
PG5 input (port)
PG4 input (port)
PGCRL1 PG3 input (port)
PG2 input (port)
PG1 input (port)
PG0 input (port)
Setting of Mode Bits (PGnMD[3:0])
0001
0010
0011
0100
Function 2
(Related Module)
Function 3
(Related Module)
Function 4
(Related Module)
Function 5
(Related Module)
VIHSYNC input
(Video-In)
AN7 input (ADC)
DA1 output (DAC) 
VIVSYNC input
(Video-In)
AN6 input (ADC)
DA0 output (DAC) 

AN5 input (ADC)


VICLKENB input
AN4 input (ADC)


(Video-In)
IRQ3 input (INTC) AN3 input (ADC)
SD_WP input (SDHI) TCLKD input (MTU2)
IRQ2 input (INTC) AN2 input (ADC)
SD_CD input (SDHI) TCLKC input (MTU2)
IRQ1 input (INTC) AN1 input (ADC)

TCLKB input (MTU2)
IRQ0 input (INTC) AN0 input (ADC)
FRB input (FLCTL) TCLKA input (MTU2)
Rev. 1.00 Mar. 14, 2008 Page 1582 of 1984
REJ09B0351-0100