SH7265 Datasheet, PDF (271/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 8 User Break Controller (UBC)
Bit
6
5
4 to 0
Bit Name
PCB1
PCB0

Initial
Value
0
0
All 0
R/W Description
R/W PC Break Select 1
Selects the break timing of the instruction fetch cycle
for channel 1 as before or after instruction execution.
0: PC break of channel 1 is generated before
instruction execution.
1: PC break of channel 1 is generated after instruction
execution.
R/W PC Break Select 0
Selects the break timing of the instruction fetch cycle
for channel 0 as before or after instruction execution.
0: PC break of channel 0 is generated before
instruction execution.
1: PC break of channel 0 is generated after instruction
execution.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Mar. 14, 2008 Page 235 of 1984
REJ09B0351-0100