SH7265 Datasheet, PDF (1593/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 29 AESOP
Bit
3 to 0
Initial
Bit Name Value
SF[3:0] 0100
R/W Description
R/W Sampling Frequency
These bits set the sampling frequency.
0100: 44100 Hz
29.3.12 Setting-Predetermined Register 4 (TBRSR)
This register sets the default tone control value. When AAC encoding processing is executed with
the AESOP, this register should be set to H'0DEE094A.
29.3.13 Header Setting Register (HEADR)
HEADR is a 32-bit readable/writable register that sets the ADTS format header for AAC
encoding.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
HEAD
SEL
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Bit
Bit Name
31 to 1 
Initial
Value
All 0
0
HEADSEL 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W AAC Header Format Select
Selects AAC header format.
0: None (raw data)
1: ADTS format
Rev. 1.00 Mar. 14, 2008 Page 1557 of 1984
REJ09B0351-0100