SH7265 Datasheet, PDF (164/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 5 Clock Pulse Generator (CPG)
Initial
Bit
Bit Name Value R/W Description
2 to 0
PFC[2:0] 100 R/W Peripheral Clock Frequency Division Ratio (Pφ)
/101*
Specify the division ratio for the peripheral clock, which is
used in division of the output frequency of the PLL circuit.
• Clock modes 0, 1, and 2
000: Reserved (setting prohibited)
001: Reserved (setting prohibited)
010: Reserved (setting prohibited)
011: Reserved (setting prohibited)
100: × 1/6 (initial value)
101: × 1/8
110: × 1/12
• Clock mode 3
000: Reserved (setting prohibited)
001: Reserved (setting prohibited)
010: Reserved (setting prohibited)
011: Reserved (setting prohibited)
100: × 1/6
101: × 1/8 (initial value)
110: × 1/12
Note: * The initial value depends on clock mode.
Rev. 1.00 Mar. 14, 2008 Page 128 of 1984
REJ09B0351-0100