SH7265 Datasheet, PDF (1291/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
12
DTCH
11
ATTCH
10 to 7 
Initial
Value
0
R/W
R/W*¹
0
R/W*¹
Undefined R
Description
PORT0 USB Disconnection Detection Interrupt Status
This bit is set to 1 on detecting USB bus
disconnection on PORT0. This module detects bus
disconnection based on USB Specification 2.0.
After detecting a DTCH interrupt, this module
performs control described below (irrespective of the
setting of the corresponding interrupt enable bit).
Terminate all the pipes in which communications on
PORT0 are currently carried out and enter a state
waiting for bus connection to PORT0 (wait for an
ATTCH interrupt).
(1) Modifies the UACT bit for PORT0 to 0.
(2) Puts PORT0 into the idle state.
0: DTCH interrupt has not occurred
1: DTCH interrupt has occurred
PORT0 USB Connection Detection Interrupt Status
When the host controller function is selected, this
module detects a PORT0 ATTACH interrupt on
generation of a J-state or K-state of the full-speed or
low-speed level signal for 2.5 µs on PORT0, and sets
this bit to 1. Detailed detection condition is as follows:
(1) Change from a K-state, SEO or SE1 to a J-state,
and continuation in the J-state for 2.5 µs
(2) Change from a J-state, SEO or SE1 to a K-state,
and continuation in the K-state for 2.5 µs
0: ATTCH interrupt has not occurred
1: ATTCH interrupt has occurred
Reserved
Undefined values are read from these bits. The write
value should always be 0.
Rev. 1.00 Mar. 14, 2008 Page 1255 of 1984
REJ09B0351-0100