SH7265 Datasheet, PDF (1608/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 29 AESOP
Procedure for processing status end interrupt processing
Confirm that input PCM data of the final frame has been transferred: Amount of transferred data is managed by the CPU.
Set EVCLR to H'00000000: Clear the interrupt source.
Set EVMSR to H'00000100: Set the interrupt source.
AESOP interrupt processing
Confirm an AESOP interrupt.
Set EVMSR to H'00000000: Disable the interrupt source.
Set DMA transfer: Suspend the transfer.
Set EVCLR to H'00000000: Clear the interrupt source.
Enter the following steps after 10 cycles (number of the AESOP clock cycles)
Read EVCDO (bit 1) in EVCLR.
When bit 1 (EVCDO) = 0 (no data being transferred)
When bit 1 (EVCDO) = 1 (data being transferred)
Set SDFOR to H'00000001: Set forcible transfer.
Set DMA transfer: Restart transfer.
Read SDBTR: Confirm the amount of data to be forcibly transferred
0: No data transfer
Set DMA transfer: Specify amount of data to be forcibly
transferred and transfer settings
Confirm a DMA trasnfer end interrupt.
DMA interrupt processing
Set SDFOR to H'00000001: Set forcible transfer.
Confirm a DMA transfer end interrupt.
Read SDBTR: Confirm the amount of data to be forcibly transferred.
0: No data transfer
Set DMA transfer: Specify amount of data to be forcibly transferred
and transfer settings
Confirm a DMA transfer end interrupt.
Read SDFOR: Cancel the forcible trasnfer (automatically cleared to 0 when transfer is performed normally for the number of times of transfers).
End
Figure 29.10 Processing Status End Interrupt Processing Flowchart
(when a Timer Interrupt is Not in Use)
Rev. 1.00 Mar. 14, 2008 Page 1572 of 1984
REJ09B0351-0100