SH7265 Datasheet, PDF (220/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 Interrupt Controller (INTC)
7.3.11 Inter-processor Interrupt Enable Registers (C0IPER, C1IPER)
C0IPER and C1IPER are 16-bit registers that enable or disable inter-processor interrupts of each
interrupt priority level. The interrupt controller decides whether to accept interrupts, according to
the inter-processor interrupt enable settings. C0IPER enables or disables interrupts to CPU0, while
C1IPER enables or disables interrupts to CPU1.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CIPE15 CIPE14 CIPE13 CIPE12 CIPE11 CIPE10 CIPE9 CIPE8 -
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
R
R
R
R
R
Bit
15
14
13
12
11
10
9
8
7 to 0
Initial
Bit Name Value
CIPE15 0
CIPE14 0
CIPE13 0
CIPE12 0
CIPE11 0
CIPE10 0
CIPE9 0
CIPE8 0

All 0
R/W Description
R/W Inter-processor Interrupt Enable
R/W These bits enable or disable inter-processor interrupt
R/W ^{requests of priority levels 15 to 8.}
R/W ^{0: Inter-processor interrupt is disabled.}
1: Inter-processor interrupt is enabled.
R/W
R/W
R/W
R/W
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 14, 2008 Page 184 of 1984
REJ09B0351-0100