SH7265 Datasheet, PDF (367/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus State Controller (BSC)
(11) Clock Stop Control Signal
The SDRAMC is provided with a clock stop control function, which can stop CKIO in deep-
power-down mode. The function can be enabled or disabled using the DCKSEN bit in the
SDRAM clock stop control signal setting register (SDCKSCNT).
CKIO runs continuously if the clock stop control function is disabled.
If the clock stop control function is enabled, CKIO stops or restarts operation in synchronization
with transition to or from deep-power-down mode.
In transition to deep-power-down mode, CKIO is stopped (low level) after the deep-power-down
entry command is issued. In recovery from deep-power-down mode, a deep-power-down exit
command is issued when the clearing of the DDPD bit to 0 is accepted by SDRAMC, and CKIO
restarts operating.
DCKSC, the period from the issuance of deep power-down entry (or exit) command until CKIO
stops (or restarts) operating, can be set using the SDRAM clock stop control signal setting register.
Figures 10.23 and 10.24 show the operation timing of the clock stop control function.
CKIO
SDRAM command
DPD
CKE
Deep-power-down mode
DCKSC
DDPDST bit value changes to 0
DPD: Deep-power-down entry command
Figure 10.23 Clock Stop Control Function Operation Timing
(Transition to Deep-Power-Down Mode)
Rev. 1.00 Mar. 14, 2008 Page 331 of 1984
REJ09B0351-0100