SH7265 Datasheet, PDF (452/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.19 DMA Two-Dimensional Addressing Next Row Offset Register (DM2DNROSTm)
DM2DNROSTm is a register used to set the offset for calculating the start address of the next row
in two-dimensional addressing.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DNROST[31:16]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DNROST[15:0]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 0
DNROST Undefined
[31:0]
R/W DMA2D Next Row Offset Byte Count
In two-dimensional addressing, these bits are used to set
the number of bytes to be added to the current source or
destination address to calculate the start address of the next
row when DMA transfer of one row in one block ends. Set a
two’s complement number in these bits.
Rev. 1.00 Mar. 14, 2008 Page 416 of 1984
REJ09B0351-0100