C8051F93X Datasheet, PDF (94/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
7.2. Comparator Outputs
When a comparator is enabled, its output is a logic 1 if the voltage at the positive input is higher than the
voltage at the negative input. When disabled, the comparator output is a logic 0. The comparator output is
synchronized with the system clock as shown in Figure 7.2. The synchronous “latched” output (CP0, CP1)
can be polled in software (CPnOUT bit), used as an interrupt source, or routed to a Port pin through the
Crossbar.
The asynchronous “raw” comparator output (CP0A, CP1A) is used by the low power mode wakeup logic
and reset decision logic. See the Power Options chapter and the Reset Sources chapter for more details
on how the asynchronous comparator outputs are used to make wake-up and reset decisions. The
asynchronous comparator output can also be routed directly to a Port pin through the Crossbar, and is
available for use outside the device even if the system clock is stopped.
When using a Comparator as an interrupt source, Comparator interrupts can be generated on rising-edge
and/or falling-edge comparator output transitions. Two independent interrupt flags (CPnRIF and CPnFIF)
allow software to determine which edge caused the Comparator interrupt. The comparator rising-edge and
falling-edge interrupt flags are set by hardware when a corresponding edge is detected regardless of the
interrupt enable state. Once set, these bits remain set until cleared by software.
The rising-edge and falling-edge interrupts can be individually enabled using the CPnRIE and CPnFIE
interrupt enable bits in the CPTnMD register. In order for the CPnRIF and/or CPnFIF interrupt flags to gen-
erate an interrupt request to the CPU, the Comparator must be enabled as an interrupt source and global
interrupts must be enabled. See the Interrupt Handler chapter for additional information.
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
Analog Input Multiplexer
Px.x
CP1 +
Px.x
Px.x
CP1 -
Px.x
VDD
CPT0MD
CP1
Interrupt
CP1
Rising-edge
CP1
Falling-edge
+
-
GND
D ^SET Q
Q CLR
D ^SET Q
Q CLR
(SYNCHRONIZER)
(ASYNCHRONOUS)
Reset
Decision
Tree
Interrupt
Logic
CP1
Crossbar
CP1A
Figure 7.2. Comparator 1 Functional Block Diagram
94
Rev. 1.3