C8051F93X Datasheet, PDF (219/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 21.1. Port I/O Assignment for Analog Functions
Analog Function
Comparator1 Input
Voltage Reference (VREF0)
Analog Ground Reference (AGND)
Current Reference (IREF0)
External Oscillator Input (XTAL1)
External Oscillator Output (XTAL2)
Potentially
Assignable Port Pins
P0.0–P2.6
P0.0
P0.1
P0.7
P0.2
P0.3
SFR(s) used for
Assignment
CPT1MX, PnSKIP
REF0CN, PnSKIP
REF0CN, PnSKIP
IREF0CN, PnSKIP
OSCXCN, PnSKIP
OSCXCN, PnSKIP
Rev. 1.3
219