C8051F93X Datasheet, PDF (30/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 3.1. Pin Definitions for the C8051F92x-C8051F93x (Continued)
Name
P2.1*
Pin Numbers
Type Description
‘F920/30 ‘F921/31
15
D I/O or Port 2.1. See Port I/O Section for a complete description.
A In
AD9*
P2.2*
14
D I/O Address/Data 9.
D I/O or Port 2.2. See Port I/O Section for a complete description.
A In
AD10*
P2.3*
13
D I/O Address/Data 10.
D I/O or Port 2.3. See Port I/O Section for a complete description.
A In
AD11*
P2.4*
12
D I/O Address/Data 11.
D I/O or Port 2.4. See Port I/O Section for a complete description.
A In
ALE*
P2.5*
11
D O ^{Address Latch Enable.}
D I/O or Port 2.5. See Port I/O Section for a complete description.
A In
RD*
P2.6*
8
D O ^{Read Strobe.}
D I/O or Port 2.6. See Port I/O Section for a complete description.
A In
WR*
DO
*Note: Available only on the C8051F920/30.
Write Strobe.
30
Rev. 1.3