C8051F93X Datasheet, PDF (117/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
10.2. Configuring the External Memory Interface for Off-Chip Access
Configuring the External Memory Interface for off-chip memory space access consists of four steps:
1. Configure the Output Modes of the associated port pins as either push-pull or open-drain
(push-pull is most common) and skip the associated pins in the Crossbar (if necessary).
See Section “21. Port Input/Output” on page 216 to determine which port pins are associated
with the External Memory Interface.
2. Configure port latches to “park” the EMIF pins in a dormant state (usually by setting them to
logic 1).
3. Select the memory mode (on-chip only, split mode without bank select, split mode with bank
select, or off-chip only).
4. Set up timing to interface with off-chip memory or peripherals.
Each of these five steps is explained in detail in the following sections. The configuration selection bits are
located in the EMI0CF register shown in SFR Definition 10.2.
10.3. External Memory Interface Port Input/Output Configuration
When the External Memory Interface is used for off-chip access, the associated port pins are shared
between the EMIF and the GPIO port latches. The Crossbar should be configured not to assign any
signals to the associated port pins. In most configurations, the RD, WR, and ALE pins need to be skipped
in the Crossbar to ensure they are controlled by their port latches. See Section “21. Port Input/Output” on
page 216 to determine which port pins are associated with the External Memory Interface.
The External Memory Interface claims the associated Port pins for memory operations ONLY during the
execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port
pins reverts to the Port latches. The Port latches should be explicitly configured to “park” the
External Memory Interface pins in a dormant state, most commonly by setting them to a logic 1.
During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the
drivers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). For port
pins acting as Outputs (Data[7:0] during a WRITE operation, for example), the External memory interface
will not automatically enable the output driver. The output mode (whether the pin is configured as Open-
Drain or Push-Pull) of bi-directional and output only pins should be configured to the desired mode when
the pin is being used as an output.
The Output mode of the Port pins while controlled by the GPIO latch is unaffected by the External Memory
Interface operation, and remains controlled by the PnMDOUT registers. In most cases, the output
modes of all EMIF pins should be configured for push-pull mode.
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