C8051F93X Datasheet, PDF (64/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 4.13. Comparator Electrical Characteristics
V_DD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted.
Parameter
Conditions
Min
Response Time:
CP0+ – CP0– = 100 mV —
Mode 0, V_DD = 2.4 V, V_CM* = 1.2 V _{CP0+ – CP0– = –100 mV —}
Response Time:
CP0+ – CP0– = 100 mV —
Mode 1, V_DD = 2.4 V, V_CM* = 1.2 V _{CP0+ – CP0– = –100 mV —}
Response Time:
CP0+ – CP0– = 100 mV —
Mode 2, V_DD = 2.4 V, V_CM* = 1.2 V _{CP0+ – CP0– = –100 mV —}
Response Time:
CP0+ – CP0– = 100 mV —
Mode 3, V_DD = 2.4 V, V_CM* = 1.2 V _{CP0+ – CP0– = –100 mV —}
Common-Mode Rejection Ratio
Inverting or Non-Inverting Input
Voltage Range
Input Capacitance
Input Bias Current
—
–0.25
—
—
Input Offset Voltage
–7
Power Supply
Power Supply Rejection
—
VDD = 3.6 V
—
Power-up Time
VDD = 3.0 V
—
VDD = 2.4 V
—
Supply Current at DC
VDD = 1.8 V
—
Mode 0
—
Mode 1
—
Mode 2
—
Mode 3
—
*Note: Vcm is the common-mode voltage on CP0+ and CP0–.
Typ
130
200
210
410
420
1200
1750
6200
1.5
—
Max
—
—
—
—
—
—
—
—
4
V_DD + 0.25
Units
ns
ns
ns
ns
ns
ns
ns
ns
mV/V
V
12
—
pF
1
—
nA
—
+7
mV
0.1
—
mV/V
0.6
—
µs
1.0
—
µs
1.8
—
µs
10
—
µs
23
—
µA
8.8
—
µA
2.6
—
µA
0.4
—
µA
64
Rev. 1.3