C8051F93X Datasheet, PDF (276/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 24.1. SPInCFG: SPI Configuration
Bit
Name
Type
Reset
7
SPIBSY
R
0
6
MSTEN
R/W
0
5
CKPHA
R/W
0
4
CKPOL
R/W
0
3
SLVSEL
R
0
2
NSSIN
R
1
1
SRMT
R
1
0
RXBMT
R
1
SFR Addresses: SPI0CFG = 0xA1, SPI1CFG = 0x84 
SFR Pages: SPI0CFG = 0x0, SPI1CFG = 0x0
Bit
Name
Function
7
SPIBSY SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
6
MSTEN Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
5
CKPHA SPI Clock Phase.
0: Data centered on first edge of SCK period.^*
1: Data centered on second edge of SCK period.^*
4
CKPOL SPI Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
3
SLVSEL Slave Selected Flag.
Set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It
is cleared to logic 0 when NSS is high (slave not selected). This bit does not indi-
cate the instantaneous value at the NSS pin, but rather a de-glitched version of the
pin input.
2
NSSIN NSS Instantaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
1
SRMT
Shift Register Empty (valid in slave mode only).
Set to logic 1 when data has been transferred in/out of the shift register, and there
is no data is available to read from the transmit buffer or write to the receive buffer.
Set to logic 0 when a data byte is transferred to the shift register from the transmit
buffer or by a transition on SCK. Note: SRMT = 1 in Master Mode.
0
RXBMT Receive Buffer Empty (valid in slave mode only).
Set to logic 1 when the receive buffer has been read and contains no new informa-
tion. If there is new information available in the receive buffer that has not been
read, this bit will return to logic 0. Note: RXBMT = 1 in Master Mode.
*Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 24.1 for timing parameters.
276
Rev. 1.3