C8051F93X Datasheet, PDF (222/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
P0
P1
P2
SF Signals
PIN I/O
TX0
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 12 3 4567
RX0
SCK (SPI1)
MISO (SPI1)
MOSI (SPI1)
NSS* (SPI1)
(*4-Wire SPI Only)
SCK (SPI0)
MISO (SPI0)
MOSI (SPI0)
NSS* (SPI0)
(*4-Wire SPI Only)
SDA
SCL
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 000X
P0SKIP[0:7]
P1SKIP[0:7]
P2SKIP[0:7]
Figure 21.3. Crossbar Priority Decoder with No Pins Skipped
222
Rev. 1.3