C8051F93X Datasheet, PDF (182/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 16.2. DC0CF: DC-DC Converter Configuration
Bit
Name
Type
Reset
7
Reserved
R
0
6
5
CLKDIV[1:0]
R/W
R/W
0
0
4
AD0CKINV
R/W
0
3
CLKINV
R/W
0
2
ILIMIT
R/W
0
1
VDDSLP
R/W
0
0
CLKSEL
R/W
0
SFR Page = 0x0; SFR Address = 0x96
Bit Name
7 Reserved Reserved.
Read = 0b; Must write 0b.
6:5 CLKDIV[1:0] _{DC-DC Clock Divider.}
Function
Divides the dc-dc converter clock when the system clock is selected as the clock
source for dc-dc converter. These bits are ignored when the dc-dc converter is
clocked from its local oscillator.
00: The dc-dc converter clock is system clock divided by 1.
01: The dc-dc converter clock is system clock divided by 2.
10: The dc-dc converter clock is system clock divided by 4.
11: The dc-dc converter clock is system clock divided by 8.
4 _AD0CKINV ADC0 Clock Inversion (Clock Invert During Sync).
Inverts the ADC0 SAR clock derived from the dc-dc converter clock when the SYNC
bit (DC0CN.3) is enabled. This bit is ignored when the SYNC bit is set to zero.
0: ADC0 SAR clock is inverted.
1: ADC0 SAR clock is not inverted.
3 CLKINV _{DC-DC Converter Clock Invert.}
Inverts the system clock used as the input to the dc-dc clock divider.
0: The dc-dc converter clock is not inverted.
1: The dc-dc converter clock is inverted.
2
ILIMIT _{Peak Current Limit Threshold.}
Sets the threshold for the maximum allowed peak inductor current. See Table 16.1
for peak inductor current levels.
0: Peak inductor current is set at a lower level.
1: Peak inductor current is set at a higher level.
1 VDDSLP _{VDD-DC+ Sleep Mode Connection.}
Specifies the power source for VDD/DC+ in Sleep Mode when the dc-dc converter is
enabled.
0: VDD-DC+ connected to VBAT in Sleep Mode.
1: VDD-DC+ is floating in Sleep Mode.
0 CLKSEL _{DC-DC Converter Clock Source Select.}
Specifies the dc-dc converter clock source.
0: The dc-dc converter is clocked from its local oscillator.
1: The dc-dc converter is clocked from the system clock.
16.10. DC-DC Converter Specifications
See Table 4.14 on page 66 for a detailed listing of dc-dc converter specifications.
182
Rev. 1.3