C8051F93X Datasheet, PDF (27/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
3. Pinout and Package Definitions
Name
VBAT
V_DD /
DC+
DC– /
Table 3.1. Pin Definitions for the C8051F92x-C8051F93x
Pin Numbers
‘F920/30 ‘F921/31
5
5
3
3
Type
P In
P In
Description
Battery Supply Voltage. Must be 0.9 to 1.8 V in single-cell
battery mode and 1.8 to 3.6 V in dual-cell battery mode.
Power Supply Voltage. Must be 1.8 to 3.6 V. This supply
voltage is not required in low power sleep mode. This
voltage must always be > VBAT.
P Out
Positive output of the dc-dc converter. In single-cell battery
mode, a 1 µF ceramic capacitor is required between DC+
and DC–. This pin can supply power to external devices
when operating in single-cell battery mode.
1
1
P In DC-DC converter return current path. In single-cell battery
mode, this pin is typically not connected to ground.
GND
G In dual-cell battery mode, this pin must be connected
directly to ground.
GND
2
2
G Required Ground.
DCEN
4
4
P In DC-DC Enable Pin. In single-cell battery mode, this pin
must be connected to VBAT through a 0.68 µH inductor.
RST/
G In dual-cell battery mode, this pin must be connected
directly to ground.
6
6
D I/O Device Reset. Open-drain output of internal POR or V_DD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. A 1 k to 5 k pullup
to V_DD is recommended. See Reset Sources Section for a
complete description.
C2CK
D I/O Clock signal for the C2 Debug Interface.
P2.7/
7
7
D I/O Port 2.7. This pin can only be used as GPIO. The Crossbar
cannot route signals to this pin and it cannot be configured
as an analog input. See Port I/O Section for a complete
description.
C2D
D I/O
XTAL3
10
9
A In
XTAL4
9
8
A Out
*Note: Available only on the C8051F920/30.
Bi-directional data signal for the C2 Debug Interface.
SmaRTClock Oscillator Crystal Input.
See Section 20 for a complete description.
SmaRTClock Oscillator Crystal Output.
See Section 20 for a complete description.
Rev. 1.3
27